1. Field of the Invention
The present invention generally relates to a method for fabricating a bottom electrode of a dynamic random access memory (DRAM) capacitor. More specifically, the present invention relates to a method that can enlarge the surface area of the bottom electrode of a DRAM capacitor.
2. Description of the Related Art
A DRAM cell is constructed of a MOS transistor and a capacitor, wherein the charge storage ability of the capacitor is utilized to store information. Because of charge leakage paths, such as the inverse bias leakage path of a PN junction, it is necessary to recharge or discharge the capacitor of a cell at regular intervals to keep the stored information correct. This is called refreshing. The longer the refresh interval, the more stable the stored information. Furthermore, the power consumption of the DRAM cell is less.
One way to prolong the refresh interval is to increase the capacitance of the capacitor. This can be accomplished by enlarging the surface area of the bottom electrode of the capacitor. FIG. 1 is a cross-sectional view of a capacitor using a fin structure to increase the surface area of the bottom electrode. The fin structure has an inter-poly dielectric layer 12 and a poly plug 14 formed therein to act as a node contact. A bottom electrode superposing on the poly plug 14 has a main stem 16 and an annular ring 18. The main stem 16 and the annular ring 18 are usually made of amorphous silicon doped with phosphorous. An inter-plate dielectric layer 22 electrically separates the top electrode 20 and the bottom electrode. As shown in FIG. 1, the annular ring 18 enlarges the surface area of the bottom electrode.
As illustrated in FIG. 2, hemispherical grains can be applied to the fin structure of the bottom electrode in FIG. 1 to further enlarge the surface area. The distended surfaces of the hemispherical grains increase the surface area of the bottom electrode. The larger the diameters of the hemispherical grains, the larger the capacitance.
The diameter of a hemispherical grain has strong correlation with the impurity concentration of the amorphous silicon at the location where the hemisphere grain grows. The lower the impurity concentration, the larger the diameter of the hemispherical grain and the larger the capacitance of the capacitor. However, a bottom electrode with hemispherical grains having large diameters has an increased probability of contacting and shorting with an adjacent bottom electrode. Further, if the impurity concentration of the amorphous silicon is lessened to grow large hemispherical grains, the depletion region of the surface of the hemispherical grains will be enlarged. This result decreases the capacitance.